VLSI Design Automation: Tools and Techniques for Enchancing Circuit Performance and Reliability
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Abstract
This study proposes a reinforcement learning (RL) approach to the VLSI design automation problem, with a view to improving the key metrics of timing, power, and area. These metrics are often conflicting and interdependent, and traditional design techniques struggle to address them, leading to the use of machine learning. The proposed RL model achieves the critical path delay, power consumption and layout area minimization by adjusting the gate sizing and placement in real time. The model offered considerable improvements in performance, with an 18% improvement in timing delay, 22% in power consumption, and 12% in area efficiency. Moreover, it provided good resilience to process, voltage and temperature (PVT) variations, which is crucial for maintaining stable operation. Comparing with traditional methods and recent works based on RL, the benefits of an integrated and multi-objective RL framework are demonstrated. This work proves that reinforcement learning is a powerful technique that can be applied to VLSI design automation and help to solve numerous challenges and improve high-performance circuit design.
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