Processor Performance Simulation Application with X86 Architecture for Bimodal Insertion Policy (BIP) Cache

Abstract

This research focuses on the implementation and evaluation of the Bimodal Insertion Policy (BIP) as a cache replacement policy on the x86 microprocessor architecture, which was developed by Intel and is widely used in desktop computers, laptops, and servers. Cache serves as temporary storage to reduce application load time and increase machine execution speed if well designed. In modern processors, there are three types of cache: L1, L2, and L3. The commonly used cache replacement algorithm, the Least Recently Used (LRU), has drawbacks such as implementation complexity and suboptimal performance on certain access patterns. Alternatively, BIP offers better efficiency by sparsely inserting data into the Most Recently Used (MRU) position and controlling the percentage of incoming data through a bimodal throttle parameter (ϵ). This study uses the gem5 simulator to simulate BIP and compare its performance against LRU regarding cache hit and cache miss. The simulation results show that BIP improves cache efficiency by reducing cache misses and increasing cache hits compared to LRU, and offers a simpler implementation. However, there are some limitations in this research, such as limited test scenarios and variables that are difficult to fully control. This research is expected to contribute to a better understanding of cache management algorithms and improve the efficiency of computer systems.