Test and Power-Aware Partitioning of 3d Ics

Abstract

Minimizing test time and optimizing test power consumption are major challenges in the testing of three-dimensional integrated circuits (3D ICs), particularly when limited Through-Silicon Vias (TSVs) are involved. To improve the effectiveness of 3D IC testing, this paper presents a novel methodology that combines test power-aware optimization with session-based test scheduling. The suggested method reduces test time and TSV usage without sacrificing test power efficiency by combining the advantages of power-aware constraints and session-based core scheduling. ITC'02 benchmarks were used to test the methodology, and the results show a significant improvement over previous method. For instance, the p93791 benchmark test time with a TAM width of 64 was lowered from 494,236 cycles in previous methods to 465,351 cycles. TSV count was also decreased; for example, for the p93791 benchmark with a TAM width of 16, TSV count decreased significantly from 387 to 200. These enhancements demonstrate how well the combined scheduling strategy works to maximize test performance while consuming the fewest resources. This approach offers significant advantages for upcoming designs by offering a scalable and well-balanced solution to the challenges associated with 3D IC testing.