Design and Performance Analysis of a Low Jitter Charge Pump-Phase Locked Loop Architecture and Loop Filter in CMOS Process

Abstract

Phase-locked loop technology has made a substantial contribution to the development of communication and data transmission technologies. Moreover, several recent studies in phase-locked loop systems and state-of-the-art IC technology makes phase-locked loop devices essential system components. For usage in Phase Lock Loop (PLL) systems, a circuit for a tri-state charge pump and a circuit for a low pass filter of second order were devised. The non-ideal effects, such charge sharing and current mismatch, are lessened by the suggested design. It could be reduced by giving the two switches UP and DOWN equal values. Conversely, the outcome of low pass filter condition is found by the charge pump's output. The suggested design has been simulated. We used Cadence TM Spectra for our simulations. The charging or discharging curves of the load capacitor exhibit a clear rise in slope in between the condition of pump up and pump down, as demonstrated by the simulation results.