Enhanced Low Power Carry-Select Adder using Transmission Gate Logic

Abstract

Power reduction strategies are becoming increasingly significant in low power VLSI applications.  A digital circuit called an adder is utilized in numerous applications, such as DSP and microprocessors, to execute addition operations.  This work presents the design of a low power XNOR gate that utilizes transmission gate logic and is implemented in Carry Select Adder for low power VLSI applications. Simulation is performed using Tanner tool at 180nm technology. Power, latency, and layout area were among the performance metrics that were compared to the circuits that were already in effect. It has been determined that the current approach offers a notable improvement in terms of power and speed when compared to the current designs.