Reduced Switch Count Seven Level Inverter Topology for Standalone Applications.

Abstract

Recently, multilevel inverter (MLI) topologies gaining their popularity because of compact size, lower (dv/dt) stress, higher efficiency, and lower THD. But they are having limitations in using more devices, capacitors, and complex control. This paper presents a seven-level inverter topology with a reduced number of switches and inherits the principle of the switching capacitor technique for voltage level boosting. This proposed topology has the property of the self-balancing of capacitors. This inverter topology is controlled with the level shifted PWM technique. Dynamic performance of the topology is also addressed. The proposed circuit is also distinguished from conventional MLIs in terms of the number of components used like switches, diodes, capacitors, losses, and THD. Simulation results of the proposed circuit is validated with the help of MATLAB/Simulink.