A Comprehensive Survey and Comparison on Pipelined RISC System Architectures

Abstract

In the modern world, processors are crucial when multiple components are housed on a single chip. Here, technology is developing quickly, and as a result, a variety of risks related to processors could arise and cause degradations in power, area, and speed. Thus, the evolution of these MIPS-RISC CPUs has improved performance. The establishment of the needed characteristics and quantities for MIPS (Micro Processor without Interlocked Pipeline Stages) is the primary topic of this study. Verilog HDL is utilized for the CPU design, Xilinx is used for synthesizing, and several simulators are used for simulation. A comparison of the outcomes for several parameters is made, which aids the intern in choosing the appropriate challenge.