Fpga Based Implementation of Ddfs for Pll

Abstract

Frequency synthesizers play a crucial role in providing stable and precise frequency sources for various electronic systems, contributing to the reliability and performance of communication and signal processing applications. A frequency synthesizer is an electronic circuit or device that generates output signals with a specified frequency. It is commonly used in communication systems, radio transmitters and receivers, radar systems, and various other electronic applications where precise and stable frequency sources are required. In this work a frequency Synthesizer is designed and developed for the specifications of output Frequency Range of 20 MHz to 100 MHz, Frequency Accuracy up to 10 Hz, High Switching Speed of 20 µSec, Low Phase Noise of 110 dBc/Hz at 10KHz from carrier, Frequency Modulation with Selectable Deviation, Frequency Chirp with Selectable Step Size, TDM mode up to 4 Pre Selected Frequencies, Fixed Frequency, FM and Chirp. The Synthesizer is digitally controllable with FTW, With the simulations Frequency Range achieved is 0-400MHz against 20 – 100 MHz, Resolution achieved is 2 Hz against 10 Hz, Phase Noise performance is 120 dBc @ 10kHz, against 110 dBc, Switching Time of 2µS against 20µS, and 4 Modes of Operations achieved successfully. Xilinx fpga 2v250fg256 is used for implementation. Number of Slices used are 1264 out of   1536 with  82% , Number of Slice Flip Flops used are 536  out of   3072 with 17% ,Number of 4 input LUTs         used are 2238  out of   3072 with 72%, Number of bonded IOBs used are 52  out of 172  with 30%, Number of GCLKs used are 3  out of  16 with 18%. Compared to other DDFS implementations, this work ensured implementation of 32-bit FTW with various modes, better utilization, low power consumption, flexible coding.