Advances in Traditional Electrical Validation of High-Speed Serial Connections Using Innovative Debugging Methods and Machine Learning Models.

Abstract

As technology continues to shrink and more heterogeneous blocks are combined into single System on a chip (SOCs), the design of high-performance integrated circuits is getting more and more difficult. In the course of silicon validation, which includes testing (Wafer Testing, Automatic Test Equipment), digital validation (Functional Data route, FSM), analogue bench validation (Electrical, Interoperability), and system validation, a number of challenges that arise from the complicated design are uncovered. The process, methods, and constraints of each domain are unique. Electrical problems that have already passed through earlier stages of design are the primary focus of analogue validation. The analogue signal or mix signal nature of IPs makes it impossible for digital validation or any of the other post-silicon domains to discover electrical flaws on its own. As a result, studies focusing on analogue bench validation have grown in prominence. Recent developments in analogue bench validation, focusing on high-speed serial interface in particular, are highlighted in the proposed study. In addition, this article summarises recent technological developments that provide avenues for further study regarding analogue bench validation.