FPGA-Based implementation of Block Cipher Security Using Electronic Codebook Mode

Abstract

This paper presents FPGA implementation of the Advanced Encryption Standard using Electronic Codebook Mode. Block ciphers, a cornerstone of cryptographic systems, are employed to encrypt fixed-size blocks of data, ensuring confidentiality in communication. The FPGA platform is utilized to optimize the encryption process, leveraging its parallel processing and high-speed capabilities. The design incorporates the key components of the block cipher algorithm, ensuring efficient execution of encryption process. The implementation is evaluated for its performance, highlighting its potential for real-time secure communication in constrained environments. Two implementation methods are employed for the ECB mode: parallel and pipeline. The parallel method achieved a maximum frequency of 264 MHz, while the pipeline system reached a maximum frequency of 189 MHz.