Design and Verification of a DDR SDRAM Memory Controller for DSP Processors Using Verilog

Abstract

Synchronous DRAM (SDRAM) is widely adopted in system designs due to its high speed, burst access capability, and pipelining features. In high-performance applications utilizing processors, the processor's built-in peripheral module typically manages the interface with SDRAM. However, for other applications, the system designer must create a dedicated controller to handle SDRAM initialization, read/write operations, and memory refresh cycles. DDR SDRAM, or Double Data Rate SDRAM, utilizes a dual-edge clocking mechanism to enable faster data transfers by transmitting data on both the rising and falling edges of the clock signal. The DDR controller serves as an intermediary between the DDR SDRAM and the processor. This paper presents the implementation of a DDR controller in Verilog, using Xilinx ISE 14.5 for the design.