Digital Implementation of High-Speed PCIe Switch

Abstract

The exponential increase in capacity and performance of Application Specific Integrated Circuits (ASICs) has made area, timing, and power consumption crucial considerations in Very Large-Scale Integration (VLSI) IC design. Logic synthesis, which translates RTL (Register-Transfer Level) designs into gate-level netlists, plays a key role in achieving the required objectives w.r.t timing and area. A bottom-up synthesis approach is employed to translate RTL descriptions into gate-level netlists, effectively bridging high-level synthesis and automated physical design. Logic Equivalency Checks (LEC) with the Cadence Conformal tool ensure functional consistency between the netlist and RTL. Evaluations at a 1 GHz operating frequency reveal that low optimization efforts lead to increased gate counts, area, and power consumption, resulting in synthesis failures. In contrast, high optimization reduces instance counts from 1.71M to 1.65M, area from 2.6M to 2.53M gates, and power from 761.51mW to 702.77mW, while effectively mitigating setup and hold violations through buffer management. The design successfully passes LEC, highlighting the importance of optimization in achieving efficient ASIC design.