Design of High-speed Area Efficient 16-bit KSA Implemented By Novel 6T-Hybrid XOR-Cell for ALU-Processors

Abstract

This paper outlines the development of a 16-bit Kogge-Stone Adder (KSA) that is both rapid and effective in terms of space use. The architecture incorporates a unique 6T-Hybrid XOR-cell specifically designed for ALU-processors. The study highlights the growing need for quicker arithmetic logic units (ALUs) in contemporary processors, which requires the creation of efficient adder designs. According to a literature analysis, the KSA is considered a highly promising option because it outperforms ordinary addition algorithms in terms of both speed and area. The methodology centers on the utilization of the KSA through the cutting-edge 6T-Hybrid XOR-cell, which improves both velocity and space effectiveness. This study presents a new 16-bit KSA that utilizes an innovative 6T-Hybrid XOR-cell. The suggested design offers superior performance in terms of rapid operation and decreases the number of transistors by 50% opposed to the standard XOR-cell. Thereby, the amount of power consumption and area gets minimized compared to the existing PPA (Brent Kung, Sklansky adder, and Ladner-Fischer) designs. Typically, KSA consists of low fan-out compared to other designs, which be calculated by log2N. The Performance parameters for XOR-cell power, 16-bit KSA are 0.967 (uW), 24.512 (uW) and delay of 0.0278 is (ns), 30.154(ns), which inference that the power and delay of the proposed designs improved by 50% compared to the conventional PPA-designs. The simulation results were collected from the Cadence virtuoso tool of 45 nm technology with a supply voltage of (Vdd) 0.8V at a frequency of 1GHz. Hence, the proposed 16-bit KSA implemented by 6T-Hybrid XOR-Cell can be effectively utilized for high-speed battery operated edge-device manufacturing which are used for IoT applications.