Design and Performance Efficiency Analysis of a Low Power 4-bit Arithmetic Logic Unit

Abstract

In this paper, a novel low-power and low-transistor-count 4-bit ALU using Gate Diffusion Input technique, which reduces dynamic power consumption. We present a comprehensive analysis and simulation of the 4-bit ALU, comparing its performance in terms of power consumption, area, and delay with CMOS and GDI techniques. The GDI technique demonstrated superior performance characteristics, particularly in power dissipation, area, and propagation delay. This study focuses on the 4-bit ALU designed with both 45nm and 32nm technology for optimal low power and minimal area. The outcome reveals that the GDI technique significantly outperforms CMOS, with a reduced transistor count by half, leading to lower delay, reduced power consumption, and increased speed. These findings suggest that the 4-bit ALU using GDI techniques is a highly viable option for low-power digital design.